There are a number of conventional processes for packaging integrated circuit (IC) devices. By way of example, many plastic IC packages utilize a metallic leadframe that has been stamped or etched from a metal sheet to provide electrical interconnects to external devices. The die may be electrically connected to the leadframe by means of bonding wires, solder bumps or other suitable electrical connections. In general, the die and portions of the leadframe are encapsulated with a molding material to protect the delicate electrical components on the active side of the die while leaving selected portions of the leadframe exposed to facilitate electrical connections to external devices, such as a printed circuit board (PCB).
At various times, package designs have been proposed that utilize a metallic foil as the electrical interconnect structure in place of the leadframe. The metallic foil is typically significantly thinner than the metal sheets or panels used to form conventional leadframes. Consequently, foil-based IC packaging methods have the potential of reducing package thickness due in part to the reduced thickness of the metallic interconnect structure.
Some of the present inventors have previously described foil-based methods of packaging integrated circuits. By way of example, U.S. patent application Ser. No. 12/133,335, entitled “Foil Based Semiconductor Package,” filed Jun. 4, 2008; U.S. patent application Ser. No. 12/195,704, entitled “Thin Foil Semiconductor Package,” filed Aug. 21, 2008; U.S. patent application Ser. No. 12/571,202, entitled “Foil Based Semiconductor Package”, filed Sep. 30, 2009; U.S. patent application Ser. No. 12/571,223, entitled “Foil Plating For Semiconductor Packaging,” filed Sep. 30, 2009; and U.S. patent application Ser. No. 12/772,896, entitled “Laser Ablation Alternative to Low Cost Leadframe Process,” filed May 3, 2010, which each describe improved foil based methods of packaging integrated circuits. Each of these prior applications is hereby incorporated by reference herein for all purposes. In some of the described processes, a foil is bonded to a substantially rigid carrier during a portion of the fabrication process in order to prevent the foil from warping. Various methods may be used to pattern the foil in a manner suitable for use in integrated circuit packages. The patterned foils are then used in the packaging process.
Although a number of foil based packaging techniques exist, there are continuing efforts to develop even more efficient designs and methods for packaging integrated circuits.